• Qualcomm Technologies
  • $121,820.00 -179,460.00/year*
  • Pomona , CA
  • Engineering
  • Full-Time
  • 801 Alicia Ct


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Overview Qualcomm is the leading fabless design company, providing hardware, software, and related services to nearly every mobile device maker and operator in the global wireless marketplace. A state-of-the-art high-performance, low-power, and area-effective standard cell library provides a strong foundation for Qualcomms multi-tier mobile SOC roadmap. The Qualcomm standard cell library team is searching for a highly qualified engineer who can lead the development of next-generation standard cell libraries for 5G mobile SOC and automotive subsystems. The candidate will define, develop, and advance standard cell libraries through a holistic method linking advanced process technologies to circuit design and to SOC design. The candidate will deliver the best-in-class library optimized for performance, power, area, and reliability. The candidate will dynamically interact with broad engineering organizations and also influence the library roadmap and development at leading foundries. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications
  • Bachelor's degree in Science, Engineering, or related field.
  • 5+ years ASIC design, verification, or related work experience.
  • Preferred Qualifications
  • 5 years of experience in standard cell and/or relevant foundation IP design and development
  • Experiences in pioneering standard cell architectures, circuits, and library development & verification methodology
  • Experiences in advanced process technology-circuit co-development
  • Experiences in developing or assessing standard cell KPI, PPA, high-sigma circuit, etc.
  • Solid understanding of advanced FinFET and next-generation CMOS devices (e.g. gate-all-around transistors)
  • Good knowledge of VLSI design flow and methodology
  • Understanding of Built-in-Reliability
  • Reliability-aware design methodology concerning thermal management, electromigration, device aging effect, Vmin, etc.
  • Deep understanding of device scaling challenges and circuit-process technology interactions applicable for cutting-edge nodes (5nm and below)
  • Experiences in or solid understanding of auto-grade standard cells
  • Proficient in standard cell development flow and tools
  • Experiences in new-design silicon validation and design for yield.
  • MS in Electrical Engineering, Solid-state Physics, or Computer Engineering
  • Preferred: Ph.D. in the above fields
  • Education Requirements Required: Bachelor's, Computer and/or Electrical Engineering
    Preferred: Master's or PhD, Computer and/or Electrical Engineering

    Keywords

    Associated topics: architecture, cadence, chip, design, digital, engg, engineer, engineer i, pc, schema

    * The salary listed in the header is an estimate based on salary data for similar jobs in the same area. Salary or compensation data found in the job description is accurate.

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