Overview Qualcomm's Mixed-Signal PHY design team is actively looking for analog and mixed-signal circuit designer to work on SerDes PHY designs. This designer will be involved in delivering next-generation PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-edge CMOS process technology nodes at 7nm and beyond. Design goals also include low-power analog designs to address Qualcomm's low-power wireless products. The primary responsibility of this position entails working within a team to deliver analog and mixed-signal transistor level circuit designs along with the physical layouts of the high speed circuits for high-speed, low-power PHY SerDes blocks. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.
Master's Degree plus 3-15 years of analog design experience - or - PhD with analog design internship experience up to 10 years of experience plus:
Experience in designing op-amps, band gaps, differential amplifiers, LDO
Experience with VCO, PLL, Charge pump, DLL, High Speed Clock Distribution, CTLE/DFE, CDR
Experience in using SPICE simulators (Cadence Analog Artist experience is preferred).
Experience using schematic capture tools (Virtuoso preferred).
Signal integrity in high speed wireline design
Full-custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign-off
Understanding of FinFet process effects on designs and layout.
Understanding of PCIe, USB or Gigabit Ethernet protocol is highly preferred.