Overview Qualcomm CDMA Technologies (QCT), is the world leader in wireless ICs powering the majority of 3G & 4G devices and is the largest fabless semiconductor in the world. QCT's Digital ASIC design team delivers cutting edge hardware and software products that power the user experience and graphics content of the most advanced mobile devices on the market. Our Design Verification team is currently seeking applicants for graphics functional design verification positions that involve the development of corresponding test plans, designing and developing our verification environments, and applying these to verify complex GPGPU designs until coverage and performance goals are achieved. As verification is a rapidly changing field and consumes majority of the design process, developing and deploying new verification methodologies is an essential part of the work you will do. Assertions, simulation, formal verification(static property checking), HW-SW co-verification and constraint/HVL-based verification are all tools in our verification toolbox you will use on a daily basis. QCT is the largest fabless design house in the world and provides hardware, software and services to nearly every mobile device maker and operator in the wireless marketplace. Our chipsets power a variety of products; tablets, smartphones, e-readers and other devices, and our digital design teams are at the core of all of them. The environment is fast-paced and requires cross-functional interaction on a daily basis so good communication, planning and execution skills are a must. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.
Preferred Qualifications Industry experience required in the following areas:
Verification skills: test planning, test bench architecture, assertions, problem solving and debug
Constrained Random Verification experience with SystemVerilog using OVM or UVM