Digital Verification Engineer for Mixed-Signals IPs used in Qualcomm's power management chip (PMIC). IPs include ADCs, fuel gauging, charging, power management.
Digital Verification aspects include all stages of the verification process from test planning, UVM-compliant test-bench architecture, constrained-random stimulus creation, score-boarding and coverage closure.
Mixed-Signals IPs require creation, maintenance and debugging of analog circuits behavioural models.
Work includes debugging of complex embedded systems including firmware, embedded sequencers at mixed-signals IP and power management chip levels.
Work in a dynamic team environment with aggressive schedule towards metrics-based high quality target.
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.
BS plus 5 Years of Experience in ASIC Design or Verification
Education Requirements Required: Bachelor's degree in Science, Engineering, or related field. Preferred: Master's, Electrical Engineering Keywords
Associated topics: cadence, design, design engineer, engineer iii, engineer iv, h/w designer, h/w engineer, plc, rf, semiconductor
* The salary listed in the header is an estimate based on salary data for similar jobs in the same area. Salary or compensation data found in the job description is accurate.