Overview Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in.
QUALCOMM has a mission to evaluate and help commercialize advance technologies found in our chipsets including: machine learning, computer architecture and micro-architecture, modem architecture and micro-architecture, low power VLSI design, SOC modeling etc. The work environment is fast paced and dynamic so candidates must be versatile and flexible in their work assignments. The ability to learn new technical skills and a willingness to adapt to new projects is crucial.
The candidate will work as part of a team of engineers to develop innovative technologies and SOC solutions for next generation mobile/cloud-based chipsets/. Responsibilities include Developing a deep understanding of the DUT (Design-Under-Test); Development of test-plans; and Executing on the test plan and debugging. Design and development of the verification environment components Verification components to be developed may include bus functional models/agents/bus interface models, data/transaction and sequencers, bus monitors, checkers/scoreboard, coverage models, and assertion libraries. Reuse of VIP(Verification IPs) from vendor supplied or in-house libraries. Development of test-benches for block level and top-level verification. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field.
ASIC design, ASIC verification coursework or related work experience.
Verification skills: test planning, test bench architecture, assertions, problem solving and debug
Constrained Random Verification experience with SystemVerilog
Experience with verification methodologies like OVM/UVM.
Design Verification with multiple design verification cycles in ASIC flow.
Development of verification environment components bus functional models/agents/bus interface models, data/transaction and sequencers, bus monitors, checkers/scoreboard, coverage models, and assertion libraries.
Development of tests based on test-plans or functional specification.
RTL design experience and/or very strong OO programming experience is also a plus
Verification of processors and cache coherent memory systems is desirable.