Overview Qualcomm's Global SoC team is actively seeking candidates for its SOC power team. This team is responsible for validating low-power structural correctness, as well as SOC level leakage and dynamic power estimations. The role requires expertise in power related tasks like leakage & dynamic power estimations for SOC blocks, structural low power design with UPF, CLP verification at various design phases, power aware functional verification with PA-GLS etc. Ideal candidate will be able to develop power intent, run power structural checks via CLP, do leakage power estimation, do dynamic power estimation via PTPx, help with pre-silicon power related debug. Previous experience with power intent format like UPF and power structural validation tools like CLP is required. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.
Preferred Qualifications 3+ years of experience in low power ASIC design, power analysis, modeling, and tool automation