Implementation of physical design for complex (ASIC) Application Specific Integrated Circuits using state of art EDA tools such as IC compiler, Star- RCXT, Primetime, Calibre. The flow includes floor planning, placement, clock tree synthesis (CTS), routing followed by optimization and sign-off closure (multi corner extraction, timing, physical verification). Develop hierarchical Place and Route methodologies for full chip as well as block level. Methodology development compatible with advanced deep sub-micron technology nodes. Provide technical direction to other team members when necessary to achieve successful project outcomes. Interact with customers, and vendors on project need basis.
Required Bachelors or foreign equivalent in CS, Electronics, CIS, Engineering (Any), or any related field. Requires +5 years of experience in the job offered, Electronics Engineer, Physical Design Engineer, or related. Must be able to travel/relocate to various client sites throughout the U.S.
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