El Segundo,California,United States6B1DP3
Boeing Defense Space & Security seeks Mid-Level Digital ASIC/FPGA Design Engineers to support the Satellite Capabilities organization and multiple satellite product lines based in El Segundo, CA.
- Utilize high-level architectural documentation along with algorithm description and implement DSP functions for functions such as decimation, interpolation, general filtering, up-down conversion, digital beam forming, channelization, and be able to develop mathematical models in SystemVerilog to verify design implementation and develop and run scripts and make files.
- Utilize understanding of system requirements to architect block level design specifications
- Prepare detailed design documentation
- HDL coding, logical equivalency checking, static timing analysis, CDC, linting
- Integration of third-party IP
- Create self-checking and reusable testbenches from scratch
- Develop Functional Coverage Models and Closing Code Coverage
Boeing is the world's largest aerospace company and leading manufacturer of commercial airplanes and defense, space and security systems. We are engineers and technicians. Skilled scientists and thinkers. Bold innovators and dreamers. Join us, and you can build something better for yourself, for our customers and for the world.
This position must meet Export Control compliance requirements, therefore a US Person as defined by 22 C.F.R. 120.15 is required. US Person includes US Citizen, lawful permanent resident, refugee, or asylee.
Basic Qualifications (Required Skills/Experience):
- 3 or more years of experience in Digital ASIC design and verification
- Experience with ASIC development including architectural definition, and detailed design implementation and functional verification using SystemVerilog
- Experience with design architecture and detailed specification generation
Preferred Qualifications (Desired Skills/Experience):
- Self-Starter: Demonstrated ability to learn and apply new concepts quickly
- Proficiency with hardware verification languages: System Verilog, System Verilog Assertions
- Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
- Knowledge and competency in UVM: Ability to create drivers, monitors, predictors, and scoreboards
- Ability to create self-checking and reusable testbenches from scratch
- Experience developing Functional Coverage Models and Closing Code Coverage
- Proficient in scripting languages: Make, Perl, Python, etc.
- Revision Control Systems: svn, cvs, git
- Proficient in Linux Environments
- Thrive in working within a fast-paced environment and work well in a team of ASIC engineers and Subsystem engineers
- Demonstrated history of 1st pass success with ASIC designs
Typical Education and Experience
Degree and typical experience in engineering classification: Bachelor's and 5 or more years' experience, Master's degree with 3 or more years' experience or PhD degree with experience. Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry. ABET is the preferred, although not required, accreditation standard.
Yes, 10 % of the TimeSpace and LaunchIndividual ContributorNoNoStandardUnited States; The Boeing Company
Associated topics: architecture, catia, circuit, engineer iii, h/w engineer, layout, pc, pcb, plc, vlsi